New fault model analysis for embedded SRAM cell for deep submicron technologies using parasitic extraction method

A bit difficult task is to identify better fit algorithms for testing complex circuits such as SRAMs in the fast growing technology environment. Many fault models have emerged but limitations and constraints for the given test environment restrict their freedom of utilization. It is observed that majority of the existing fault models were analyzed in terms of well known March algorithms which give only the fault detection information. Scale down technologies influence the parasitic effects and this causes an additional source of faulty behavior and the present test algorithms become weak in encountering them. In this paper we propose a layout dependent method for fault detection along with fault location identification. A new fault model for SRAM is presented in which the faulty model reflects as local disturbances in the layout of the SRAM cell. Two technologies, 180nm and 120nm, are considered. Applying the proposed test method resulted in 100% fault coverage. The test results of submicron (180nm) to deep sub micron (120nm) variation levels are tabulated and analyzed. The parasitic variations are compared with that of fault free SRAM. The proposed parasitic extraction method identifies the type of fault along with its location independent of the technology (180nm and 120nm) selected.