Rebel: a clustering algorithm for look-up table FPGA's

Rebel is a new algorithm for clustering gates into k-input function blocks for look-up table field-programmable gate arrays (FPGA's). The algorithm propagates functional dependencies forward through a logic network, combining gates into clusters according to a heuristic metric. Rebel does a good job of handling reconvergent circuits, duplicating logic when it makes sense to do so, in addition, Rebel is fast, computing good clusters in near-linear time.