Optimum gate voltage search for junctionless Tunnel FET using TCAD simulations

The Structure of n type junctionless Tunnel FET is created and its characteristic is studied using TCAD simulations. The device simulations have been implemented with different voltage levels for different gate structures present in the device-gate over drain (V
_G1
) and gate over source (V
_G2
), and the transfer characteristics (I
_D
-V
_G
) are studied. Considering drive current (I
_on
)> off current (I
_off
)> I
_on
/I
_off
ratio, and subthreshold slope as metric, an optimum level of V
_G1
and V
_G2
is seen for the device.