VLSI design and comparative analysis of memory BIST controllers

In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very dense to the limits of the technology they might be caused of failures. In addition, defect types are becoming more complex and diverse and may escape detection during testing. The memory test methods should evolve to cover these defects corresponding to the target fabrication process and memory design. Built-in Self-Test (BIST) technique is a promising method for different types of test problems. In the memory BIST (MBIST) technology, there is a dedicated BIST controller which is used to implement a specific memory test algorithm when the chip under test (CUT) is in test mode. Implementation and performance comparison of three types of memory BIST architectures were done in this paper. Out of these, two types of MBIST are common but poor performance. By considering the performance parameters in terms of area and speed, a new type has been introduced. The implememtations are carried out by using Verilog hardware description language and Xilinx ISE 8.2i.