Parallel FPGA implementation of incoherent OCDMA systems

The potential advantages of optical CDMA (OCDMA) over other multi access techniques attracted considerable interest over the past decade. All-optical implementations of OCDMA are often considered to be too complex to implement especially for cost-sensitive applications. On the other hand, electronic realization of OCDMA encoders/decoders are more cost effective but its throughput is restricted by the electronic processing bottleneck. In this paper, we propose an electronic implementation of OCDMA transceivers that takes advantage of newly emerging high-speed FPGA transceiver technologies, which offer speeds of up to 28 Gb/s. Though the chip rate of the proposed OCDMA system can approach such high speeds, the encoder/decoder processing can operate at much lower speed thanks to the parallel architecture that allows chips to be processed simultaneously. The proposed design benefits from its low resource utilization, which makes it suitable for smaller, affordable FPGA devices. This is in addition to the reconfigurability of FPGA devices, which further reduce the overall system cost.