A modified approach for reconfigurable FIR filter architecture

This paper proposes a modified reconfigurable architecture for finite impulse response (FIR) filter. The proposed architecture uses shift and add unit along with modified processing element (MPE) unit. MPE units and structural adders are implemented with 4:2 compressors, which improves the performance of FIR filter. The proposed filter is implemented using gate level Verilog HDL and synthesized using Xilinx's Spartan 6's 6slx45csg324-3. The synthesis results are compared with recently published architectures and show a significant improvement in area, power and delay.