A page buffer design based on stable and area-saving embedded SRAM for flash applications

This paper presents an embedded SRAM design for page buffer applications in flash memories. The page buffer was implemented with a newly proposed self-adaptive timing control circuit, an area-saving sense-latch circuit and 6T SRAM cell unit. A 2Kb SRAM macro with area of 135µm × 180µm has been implemented and applied in a 128Mb NOR flash memory with SMIC 65nm flash memory technology. Both simulation and chip test results show that SRAM page buffer is benefitial for high density flash memory design.