A 1.5–1.9GHz phase-locked loop (PLL) frequency synthesizer with AFC and Σ-Δ modulator for Sub-GHz wireless transceiver

A 1.5–1.9GHz phase-locked loop (PLL) frequency synthesizer with automatic frequency calibration (AFC) and third-order Σ-Δ modulator for Sub-GHz wireless transceiver is presented. A LC VCO ranging from 1.5GHz to 1.9GHze is integrated on this chip to meet multiple protocols. The voltage controlled oscillator is designed with modified digital controlled capacitor array to extend tuning range while minimizing the phase noise. An automatic frequency calibration (AFC) algorithm was implemented in this synthesizer to find the appropriate control word of the capacitor array. A 20-bit third-order Σ-Δ modulator is utilized to reduce out-of-band phase noise and to meet the frequency resolution of less than 30Hz as well as agile switching time.