A 50MHz–812MHz, 700mW low-power PLL with a constant KVCO ring oscillator

This paper presents a low power phase-locked-loop (PLL) with a low variation loop bandwidth. Compared to a traditional ring oscillator based PLL, it shows a constant loop bandwidth and is insensitive to PVT variation. It is implemented by using a programmable resistor-array with multiple linear voltage-to-current (VCC) curves, which replace the traditional nonlinear one. As a result, the loop bandwidth variation is reduced and low jitter is achieved. In order to further minimize the spur of current pulse from charge pump (CP) and dividers, fully differential topology are utilized. The PLL circuits consume 0.7mA current with 1-V supply voltage in TSMC 0.13um process, and the lock range is from 50MHz to 812 MHz.