Performance study of 12-CNTFET and GDI CNTFET based full adder in HSPICE

This manuscript reports and analyzes 12-CNTFET and GDI CNTFET based full adder implementation at 32 nm level. As figures of merit, stability, power dissipation and Power Delay Product (PDP) are considered for the best overall performance. Intensive HSPICE simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based full adders. Both circuit has noticeable reduction in short current power consumption but in terms of comparison GDI CNTFET shows better performance in both power consumption and Power Delay Product (PDP) variations. The CNTFET-based One bit Full Adder cell demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.