Novel level-identifying circuit for flash multilevel memories

This paper presents a high-speed, small-area circuit specifically designed to identify the levels in the read out operation of a flash multilevel memory. The circuit is based on the analog computation of the Euclidean distance between the current read out from a memory cell and the reference currents that represent the different logic levels. An experimental version of the circuit has been integrated in a standard double-metal 0.7-/spl mu/m CMOS process with a die area of only 140/spl times/100 /spl mu/m/sup 2/. Operating under a 5-V power supply, this circuit identifies the read-out current of a memory cell, and associates it with the appropriate logic level in 9 ns.