OpenRISC-based System-on-Chip for digital signal processing

This paper presents the design and implementation of an OpenRISC-based System-on-Chip (SoC), which is composed of hardware cores implementing the Digital Signal Processing (DSP) functions: Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter and Fast Fourier Transform (FFT). The FIR-filter core is based on the transpose realization form, the IIR-filter core is based on the Second Order Sections (SOS) architecture and the FFT core is based on the Radix 22 Single Delay Feedback (R2
²
SDF) architecture. The three cores are compatible with the Wishbone SoC bus, and they were described using generic and structural VHDL. In-system hardware verification was performed by using an OpenRisc-based SoC synthesized on an Altera FPGA. Tests showed that the designed DSP cores are suitable for building SoC based on the OpenRisc processor and the Wishbone bus.