FPGA implementation of RANSAC algorithm for real-time image geometry estimation

Random Sample Consensus (RANSAC) is commonly used in many estimation tasks especially in computer vision applications due to its simplicity. This paper presents a hardware/software co-design implementation of RANSAC algorithm for real-time affine geometry estimation on a field programmable gate array (FPGA) platform. Double buffering technique is used to store and process data in pipeline. Experimental result shows that the proposed system managed to speed up the software process by about 11.4 times for 100 data points. The proposed architecture was also tested on Altera DE2-115 with 100 MHz NiosII Processor running to handle a video stream of 30 frames per second.