Design and analysis of ESOP based online testable reversible SRAM array

Memory is the fundamental building block of any digital system. Most of the portable devices used today incorporate SRAM arrays which are vital memory elements. The significant role of reversible logic in designing such circuits is to reduce or completely eliminate power dissipation. According to survey, only few design methodologies have been proposed for the SRAM array and to the best of our knowledge, no online testing has ever been performed on memory array designed using various Reversible parity preserving gates. In this paper, we have proposed the design of memory cell and SRAM array using only basic reversible logic gates, which can be extended to any size. The designed memory cell has 9.5% improvement in Quantum cost, 10.5% improvement in Delay and 20% improvement in logic depth as compared to the existing design in literature. For the proposed designs, ESOP based online testability approach is adopted and analysis of Fault coverage and delay overhead due to testing is also performed for a given m×n memory array.