A 57–66 GHz power amplifier with a linearization technique in 65-nm CMOS process

This paper presents a linearization technique with a body diode for 60-GHz power amplifier (PA). This linearization technique aims to achieve adequate linear output power as PA operating under lower power consumption. This proposed technique can benefit the reduction of total power consumption of a 60-GHz phased array. The PA is implemented in TSMC 65-nm CMOS process. At 1-V supply voltage, the measured maximum output powers are all larger than 10 dBm over 57-66 GHz. Third-order inter-modulation distortion (IMD
₃
) can be mitigated over 30 dB by the proposed linearization technique. Moreover, the improvement of IMD
₃
is larger than 25 dB among the entire operation bandwidth.