Evaluation and Modeling of Voltage Stress-Induced Hot Carrier Effects in High-Speed SiGe HBTs

Hot-carrier degradation analysis and modeling of 240/380 GHz fT/fMAX SiGe HBTs are addressed. A proper stress bias setup is proposed, suitable for the evaluation of RF performance during stress interruption. The impact of stress conditions, lateral scaling and device layout is discussed. An analytical model is proposed, which predicts base current degradation, including its dependence upon stress voltage, stress duration, and emitter geometry, and contributes to understand the physical background of the phenomena.