Design of a 6.25Gb/s adaptive decision feedback equalizer in 0.18µm CMOS technology

This paper presents a 6.25Gb/s adaptive decision feedback equalizer (DFE) for high speed backplane communication, which consists of a high-speed DFE and an adaptation engine based on Sign-Sign LMS algorithm. Half-rate structure and current mode logic are employed to pursue a high operating speed. The adaptation engine is composed of sense amplifiers (SA), a 5-bit up/down counter and a 5-bit DAC, which are implemented in CMOS logic at 781.25MHz. Designed in 0.18µm CMOS process, the equalizer has an area of 0.6×0.55mm
²
including I/O pads, and the static power consumption is 45.9mW under 1.8V power supply. Measurement results show that the proposed equalizer can adapt to signals achieved from PCB channels of different lengths, and the data rate can be up to 6.8Gb/s with horizontal eye opening of outputs larger than 0.8UI.