The ChipCflow: A Tool to Generate Hardware Accelerators Using a Static Dataflow Machine Designed for a FPGA

The execution of sections of algorithms in hardware accelerators, appears as a alternative to speed up performance with low power consumption. In this article the Chip flow project is presented, the goal of Chip flow is conversion of C code in a static dataflow machine designed for a FPGA. The conversion process is discussed and some initial results are presented. The results of Chip flow are compared with a Intel core i7 processor and modern GPU. The results of benchmarks implemented show that Chip flow is a newer alternative for the development of hardware accelerators, with a good performance with low power consumption.