A VLSI implementation of a frequency synthesizer based on a charge pump PLL

The paper presents a VLSI implementation of a frequency synthesizer based on a charge pump PLL. Indirect synthesis uses a Phase Lock Loop (PLL) architecture with a programmable frequency divider in the loop, providing a large number of frequencies from a single reference frequency. The proposed frequency synthesizer is designed for Short Range Device (SRD) applications around 433MHz and for FM radio in the (88-108)MHz frequency band. The simulations were performed in 0.18μm CMOS technology and confirm the theoretically obtained results.