Common-mode voltage reduction of three level four leg PWM converter

This paper presents a carrier-based Pulse Width Modulation (PWM) method to reduce the common-mode voltage (CMV) of the three level four leg converter. The idea of the proposed PWM method is very intuitive and easy to be understood. Based on the analysis of the Space Vector PWM (SVPWM) and the Sinusoidal PWM (SPWM) switching patterns, 4
^th
leg pole voltage of the three phase converter, so called `f pole voltage' has been manipulated to reduce the common-mode voltage. To synthesize f pole voltage for the suppression of the CMV, positive and negative pole voltage references of f leg are calculated. Also an offset voltage to prevent the distortion of a, b, c phase voltages regarding to the neutral point is deduced. Not requiring extra hardware, the proposed PWM strategy can be easily implemented in the software of the DSP based converter control system without degradation of the control performance. The three level four leg converter with the proposed PWM algorithm results in a remarkable reduction in peak-to-peak value of the CMV. The feasibility of the proposed PWM method is verified by both simulation and experimental results. From the simulation and the experimental results, the peak-to-peak value of the CMV in the proposed PWM method is 33% comparing to that in the SVPWM method, and the transition number of the CMV during a switching period in the proposed PWM method is only 25% of that in the SVPWM method.