A 40 GHz 65 nm CMOS Phase-Locked Loop With Optimized Shunt-Peaked Buffer

A 40 GHz phase-locked loop (PLL) with an optimized shunt-peaked buffer is realized in Global Foundries 65 nm CMOS technology. The shunt-peaked buffer placed in the loop eliminates the capacitive loading of the frequency divider and enhances the drive capability. Hence it is possible to use an inductorless frequency divider to reduce potential parasitics in the layout. Thanks to the simplified topology and enhanced output swing, the proposed PLL achieves a good balance among silicon area, output range and phase noise. Measurement shows that the PLL works properly from 39.5 to 41.7 GHz with a phase noise of -102.7, -112, -119 dBc/Hz at 1, 10, and 20 MHz offset from the carrier, respectively. It occupies a chip area of 0.4 mm
²
including all the testing pads and consumes 87 mW from 1.5 V and 0.8 V supply voltage including the buffers.