VLSI implementation of low -complexity Reed Solomon decoder

In this paper, a low complexity architecture of Reed-Solomon (RS) code is developed to correct errors based on truncated inversion less Berlekamp-Massey algorithm. The arithmetic operations which are used in RS code are Galois Fields (GF) addition and multiplication. This paper presents: i) RS encoder modeled using MATLAB with data encoded in the noisy channel for functional verification. ii) RS decoder modeled in Verilog HDL to recover the erroneous data. The Verilog modeled RS (255, 239) decoder has the capability of 8 symbol-errors detection and correction. The proposed decoder has been designed and synthesized for the Xilinx Spartan6 series FPGAs xc6lx16-3. The resource consumption is about 44%, and the data processing rates over 1.3Gbit/s is realized.