FPGA implementation of multiplier less matched filters to transmit video signals over satellites

In satellite transmission system, the base band data is modulated onto a carrier. Filtering takes place at number of stages during the modulation and demodulation stages. This results in signal delay and ringing. The tails which results from ringing of all the preceding pulses may combine to interfere with a particular pulse being sampled and results in Inter symbol Interference (ISI). The ringing cannot be stopped but the pulses can be shaped to overcome ISI. This is achieved by using square root raised cosine filter at both transmitter and receiver. This is called matched filtering. This also maximizes Signal to Noise ratio of the system. This paper suggests a method to implement the matched filters without using multipliers and look up tables. Thus it simplifies the design and makes it more suitable for FPGA implementation.