A new optimization strategy for CMOS device process in the era of 0.2 /spl mu/m and beyond for MPU's and ASIC's

A guideline of CMOS device development for high performance MPU's and ASIC's is discussed. The thermal runaway is found to limit lowest V/sub TH/. A new scaling rule including long metal wires is discussed, including effectiveness of optional wide lines and line-repeaters. "Wiring Channel Density", which shows the process capability of high integration, is proposed. Based on the guideline, a manufacturable 0.2 /spl mu/m CMOS device with 7-layer metal is designed. It shows 1.5 times speed-up and 4 times high integration capability without RC-delay increase.