Design of a low power CMOS 10bit flash-SAR ADC

This paper proposed a low power CMOS flash-SAR ADC which consists of a flash ADC for 2 most significant bits and a SAR ADC with capacitor DAC for 8 least significant bits. Employment of a flash ADC allows the proposed circuit to enhance the conversion speed. The SAR ADC with a capacitor DAC provides a low power dissipation. The proposed ADC consumes 136 uW with a power supply of 1 V under a 0.18 um CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2 MHz. Therefore it results in 120 fJ/step of Figure of Merit (FoM).