A study of the robustness against SEUs of digital circuits implemented with FPGA DSPs

In this paper we present an experimental validation of the reliability increase of digital circuits implemented in Xilinx
^TM
FPGAs when they are implemented using the DSPs (Digital Signal Processors) that are available in the reconfigurable device. For this purpose, we have used a fault-injection platform developed by our research group, NESSY [1]. The presented experiments demonstrate that the probability of occurrence of a SEU effect is similar both in the circuits implemented with and without using embedded DSPs. However, the former are more efficient in terms of area usage, which leads to a decrease in the probability of a SEU occurrence.