A low-power and area-efficient radiation-hard redundant flip-flop, DICE ACFF, in a 65 nm thin-BOX FD-SOI

In this paper, we propose a low-power area-efficient redundant flip-flops for soft errors, called DICE-ACFF. Its structure is based on the reliable DICE (Dual Interlocked storage CEll) and the low-power ACFF (Adaptive-Coupling Flip-Flop). It achieves lower power at lower data-activity. We designed DICE-FF and DICE-ACFF using 65 nm conventional bulk and thin-BOX FD-SOI (Silicon on Thin-BOX, SOTB) processes. Its area is twice as large as the conventional DFF. As for power dissipation, DICE ACFF achieves lower power than the conventional DFF below 20% data activity. When data activity is 0%, its power is half of the DFF. As for soft error rates DICE ACFFs are 1.5x stronger than conventional DICE FFs by circuit-level simulations to estimate critical charge. No SEU is observed on the DICE ACFF by alpha-particle irradiation at 1.2V on the bulk and and SOTB chips. The soft error rates of the DFF of the SOTB chip is 1/200 compared with that of the bulk chip.