Design of 65 nm CMOS SRAM for space applications: A comparative study

We study the design of different SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the localization of a strike. DICE cells demonstrate about 2-3 orders of magnitude lower than cross-sections for 6T-cells due to the 2-μm nodal spacing of sensitive pairs. Solid and intermittent guard rings has high effectiveness in SEL elimination.