A 24-transistor static flip-flop consisting of nors and inverters for low-power digital vlsis

In this paper, we propose a low-power circuit-shared static flip-flop (CS
²
FF) for extremely low power digital VLSIs. The CS
²
FF consists of five static NORs and two inverters (INVs). The CS
²
FF utilizes a positive edge of a buffered clock signal, which is generated from a root clock, to take data into a master latch and a negative edge of the root clock to hold the data in a slave latch. The total number of transistors is only 24, which is the same as the conventional tri-state buffer based flip flop (TBFF) used in the most standard cell libraries. SPICE simulations in 0.18-μm standard CMOS process demonstrated that our proposed CS
²
FF achieved clock-to-Q delay of 17.4 ns, setup time of 5.91 ns, hold time of 1.17 ns, and power dissipation of 15.4 nW at 1-MHz clock frequency and 0.5-V power supply. The physical design area increased by 21% and power dissipation was reduced by 26% compared with those of conventional TBFF. Our proposed CS
²
FF can operate at 0.347 V with extremely low power of 6.61 nW, 33% less than that of TBFF.