2 k gate circuits with 125 ps gate delay using GaAs HFET technology

Four digital circuits were processed with the self-aligned refractory gate process in the DARPA III GaAs pilot line. The GaAs-AlGaAs heterostructure E/D FET technology (HFET) with 1- mu m channel length and a nominal power supply of 2 V was used to implement a 32-bit ALU (arithmetic logic unit), a dual 8*8 parallel multiplier, a quad 4-bit adder, and a SRAM tester. The measured propagation delay per gate is 125 ps for the ALU and 132 ps for the multiplier.<
>