NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes

Reliability of advanced deeply scaled CMOS technologies is being threatened by time-dependent degradation mechanisms such as Negative Bias Temperature Instability (NBTI) phenomenon that cause workload-dependent shifts on a transistor's threshold voltage (VTH), and performance during its lifetime. In this study, NBTI-induced performance degradation of 32-bit adders (one of the most fundamental block of a processor's arithmetic logic unit) is investigated from the points of architectural topology, technology scaling (i.e. commercial 28, 45, 65nm nodes) and workload dependency. The selected adder architectures vary from basic to complex parallel-prefix ones. A workload-dependent, NBTI aging-aware digital design flow was developed within the industry standard EDA tool chain. NBTI model is based on the extracted Capture and Emission Time (CET) maps from the actual wafer measurements. Static Timing Analysis (STA) is performed to evaluate the performance degradation at the +3σ corner. Results on adders under the NBTI aging after 3 years show a performance loss up to 16%. NBTI aging results in the replacement of the time-zero critical path by an initially non-critical path during a circuit's lifetime. The time-zero critical path can shift to a new one with a probability of 89%. Technology scaling and the choice of process technology can impact the degradation by 2×. Finally, the performance degradation can vary up to 8.2× under workload variations.