An efficient architecture for BLMS adaptive filter based on distributed arithmetic technique

This paper deals with an efficient architecture for the implementation of finite impulse response (FIR) adaptive filter using block least mean square (BLMS) algorithm based on distributed arithmetic (DA) formulation. Normally DA-based architectures are bit-serial in nature and uses a lookup table (LUT) for the computation of both filter outputs and weight vectors of BLMS algorithm. The memory size of a LUT may be determined by the block-size, thus the number of words stored in a LUT can be 2
^L
possible values of the inner products. The proposed structure use a coefficient as addresses to read the corresponding values of stored input samples from the LUTs. The LUT contents are updated during every iteration with the block of new input samples and the past samples. During the LUT update process, only the weight vectors are needed to be shifted circularly to left hand side instead of shifting the whole LUT contents to the right hand side which minimizes the time and power consumption. The ASIC synthesis result shows that the proposed have significantly less Area-Delay Product (ADP), Energy Per Output (EPO) and Power Per Output (PPO) particularly when implemented in a higher order filter, N and higher block size, L.