Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits

With the advent of deep submicron CMOS technology, process parameter statistical variations are increasing resulting in unpredictable device behaviour. The issue is even aggravated by low power requirements which are stretching transistor operation into near/sub threshold regime. Consequently, traditional delay models fail to accurately capture the circuit behaviour. In view of this we introduce an Inverse Gaussian Distribution (IGD) based delay model, which accurately captures the delay distribution under process variations at ultra low, near or below threshold, power supply values. We demonstrate that the IGD model captures the transistor delay distribution with a greater accuracy than the traditional Gaussian one. Moreover it exhibits linear compositionality such that the key model parameters can be straightforward propagated form device/gate level to circuit level. Our simulations indicate that, when compared with Monte Carlo SPICE simulation results, it provides high accuracy, e.g., an average error less than 0.8%, 1.2%, and 1.7% for Majority Voter, XOR gate, and 16-bit Ripple Carry Adder, respectively, while providing orders of magnitude simulation time reductions.