Session Based Core Test Scheduling for 3D SOCs

Design of core based three dimensional (3D) system-on-chip (SOC) is gaining a remarkable attention in modern days' semiconductor industry. Testing of 3D SOC is considered as one of the important challenge and hence efficient test techniques are required. The objective of this paper is to design efficient test access mechanism (TAM) and test scheduling architecture of different cores of the SOC such that the overall test time of that SOC is minimized. In this work, we have proposed two session-based heuristic approaches. Experimental results are presented for several ITC'02 benchmark SOCs which show promising results for different TAM width allocation.