High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High- $\kappa $ /Metal Gate

We present a vertical gate-all-around Si nanowire (SiNW) metal-oxide-semiconductor field-effect transistor with high-κ dielectric and TiN metal gate. The process flow is fully compatible with CMOS technologies. SiNWs are fabricated by deep Si reactive ion etching, gate-stack is formed by atomic layer deposition, and metal salicide is utilized as drain contact. The fabricated p-type gate-all-around SiNW metal-oxide-semiconductor field-effect transistors that have a gate length of 320 nm exhibit excellent characteristics with I
_ON
/I
_OFF
> 10
⁴
, subthreshold slope of 87 mV/decade, and 25 mV/V of drain-induced barrier lowering. Low-temperature characteristics are also presented. The demonstrated devices have potential applications in novel low-power logic circuits and as selection transistors for 4F
²
cross-point memory cells.