Test considerations for jitter tolerance of wireline receivers

A conventional jitter tolerance test methodology for high speed serial data receivers is discussed and evaluated. A Built-in Self-Test (BIST) based methodology for jitter tolerance measurement is detailed and characterized, demonstrating improved accuracy of jitter tolerance measurements of the receiver front-end and reduced complexity by using on-chip Bit Error Rate Testing. Measurements of the BIST methodology demonstrate an improvement in jitter tolerance of up to 280 mUI at a BER of 10
⁻¹²
with a 95% confidence level in a 28nm CMOS PHY operating at 10.3125-Gbps. Differences between the two methods are detailed, and difficulties associated with the conventional method are explained.