15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET
INV
-normalized G
M,SAT,INT
of 6.7 nm.mS/µm, the Si
0.3
Ge
0.7
/ sGe pFinFETs presented in this work improve the performance by ∲90% as compared to the state-of-the-art relaxed-Ge FinFETs.