First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm

We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si
_1-x
Ge
_x
(x=0, 0.2, 0.25) nanowires, Si
_0.7
Ge
_0.3
Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. We analyse the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices are also investigated, showing a W
^-3
dependence of ON current (I
_ON
) per wire. The fabricated devices exhibit higher I
_ON
than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.