Combined architecture for generation of pulse compression sequences using FPGA

Pulse compression sequences are widely used in RADAR and Communication systems applications. One of the problems facing the radar Pulse compression sequence designer is accurate generation of the Pulse compressed wave form for transmission purpose. Earlier techniques reported in the literature for generation of Pulse compression sequences were based on Surface Acoustic Wave (SAW) and Digital Waveform Generation (DWG). These techniques have a serious drawback of limited speed. To overcome speed limitation, later FPGA based separate architectures reported in literature for generation of Binary, Ternary, Four phase, Quinquenary, and higher phase pulse compression sequences. Till now a combined architecture for generation of above said Pulse compression sequences has not reported in literature. This paper aims at development of single unique combined architecture for generation of Binary, Ternary, and four phase, Pulse compression sequences using FPGA.