An 8-bit 0.35-V 5.04-fJ/Conversion-Step SAR ADC With Background Self-Calibration of Comparator Offset

This paper reports a successive approximation register (SAR) analog-to-digital converter (ADC) based on the charge-sharing principle, which is known to be very energy efficient, but susceptible to the comparator offset. The ADC uses a new background calibration technique to cancel out the comparator mismatch and improve ADC linearity. Operation under low voltages is obtained through the use of voltage-boosted switches in the track-and-hold and the digitalto-analog converter. The techniques are demonstrated on a low-voltage low-power SAR ADC that operates from a minimum supply voltage of 350 up to 600 mV, suitable for circuits supplied by power harvesters. The prototype fabricated in a 130-nm CMOS process employs only regular-VTH transistors. It is able to convert at 3 MSps when supplied by 600 mV and at 200 kSps when supplied by 350 mV. At 350 mV, the measured effective-number-of-bits is 6.4, leading to a figure-of-merit of 5.04 fJ/conversion-step.