Innovative scaling method to minimize cost of integrated circuit packages and devices

In this paper, we have shown an analytical technique to scale the power delivery solutions for a given integrated circuit (IC) chip that can draw currents to cause enough inductive noise for the IC to fail. This scaling method will also provide the optimum package solutions to minimize the cost of IC products. This method can be very useful to determine the package and die design methodology at the initial phase of the design cycle of the chip.