The design of low complexity low power pipelined short length Winograd Fourier transforms

In this paper a novel pipelining approach applicable to Winograd Fourier transforms is presented. The novel approach makes use of reconfigurable multiplier blocks to implement the real multipliers required for the transform as well as sharing the hardware resources among additions. The additions are realized using modified forms of butterfly circuits. The novel approach is tested on a 5-point Winograd Fourier transform and the circuit area and power dissipation of the design are estimated using an in-house power estimation tool and compared to the state-of-the-rt approaches.