Reduce energy requirements by coupling a poly-phase pre-filter and cic filter in high-performance Sigma-Delta A/D converters

The CIC filter is often used as a decimating filter to simultaneously reduce bandwidth and sample rate of the time series obtained at the output of a 1-bit Sigma-Delta con-verter. The conventional motivation for using the CIC is that the filtering is performed with only registers and adders, there being no multipliers in the CIC filter chain. We note that every FIR filter processing the output of a 1-bit sigma delta convert-er can also be implemented without multipliers. The CIC filter does not take advantage of the fact that the input samples are limited to two input levels. It is possible to design FIR filters using the two level input signal to form efficient multiply free filters that compare favorably with the CIC filter. We present here a partition of the filter and down sampling task into a cascade of a polyphase pre-filter that performs a first band-width and sample rate reduction without multiplies followed by a reduced sample rate CIC filter performing the second bandwidth and sample rate reduction. Operating the second filter as a CIC at a reduced output rate reduces its workload and the bit width required by its accumulators.