A harmonic-boosted V-band divide-by-3 frequency divider in 65nm CMOS

This paper presents a low power divide-by-three injection locked frequency divider (ILFD) for the V-band implemented in 65nm CMOS technology. The divider achieves a locking range of 5.5% by using the proposed harmonic-boosting technique. The 71GHz to 75GHz locking range was measured with a maximum input power of 0dBm. The inherent MOSFET non-linearity was exploited to generate the odd-order division ratio of 3. Operating with an input frequency of 75GHz, and 1.2V supply, the divider consumes 2.04mW. The total area including pads is 0.697mm×0.664mm.