Design of delay-locked loop for wide frequency locking range

In order to increase the frequency locking range, a delay-locked loop (DLL) circuit with frequency to voltage converter (FVC) and phase select circuit is described. For the low power dissipation consideration, the circuit's bias current is keep at lower level. The simulation results show that the operating frequency range extend from 106 MHz ~ 151 MHz to 54 MHz ~ 250 MHz, and the power dissipation increases from 2.47 mW ~ 3.33 mW to 6.7 mW ~ 14 mW.