Write disturb analyses on half-selected cells of cross-point RRAM arrays

Write disturb on half-selected (HS) cells is investigated through electrical measurements and large-scale array simulations. The experimental results collected from the individual devices under constant stress voltage and consecutive pulse operation are correlated with the HS cells in large-scale arrays based on a physics-based SPICE compact model. The impact of write/read disturb on the HS cells at different locations of the arrays is analyzed. Design guidelines for the optimized array size based on the experimental data and HSPICE simulations are presented: e.g., a 16 kb array can maintain its stored data pattern for 5×10
⁶
pulses and will have 164 false bits among half-selected cells after write disturb.