Low power implementation of fast addition algorithms

As portable multimedia and communications applications emerge, the need for low power digital circuits becomes more prominent. The addition process is the most used operation in any DSP because addition is involved in all other mathematical operations. Therefore, adder design is considered critical because it influences the performance of the system in terms of power and delay. In this paper, we review some of the fast addition algorithms. We also introduce power, delay and area comparison based on a 16 bit adder implemented in each algorithm.