A dual-mode highly efficient 60 GHz power amplifier in 65 nm CMOS

This paper presents a 60 GHz power amplifier utilizing a novel technique to achieve high efficiency at high output power levels. The proposed topology provides the capability of dual mode operation. The output power of a conventional class A power amplifier will be combined with the power provided by an amplifier operating at a different class to achieve higher efficiency at higher output levels. Driver stages to provide high power gain consist of an enhanced cascode stage followed by a common source amplifier with transformer-coupled impedance matching networks. Fabricated in 65 nm CMOS process, the measured gain of the 0.32 mm2 power amplifier is 17.7 dB at 60 GHz with a wide 3dB band width of 12 GHz while consuming 378 mW from a 1.2V supply. A maximum saturated output power of 16.8 dBm is measured with the 14.5% peak power added efficiency at 60 GHz.