Ultra fast, two-bit ECC for Emerging Memories

Emerging Memories (EMs) could benefit from Error Correcting Codes (ECCs) able to correct a few errors in just a few nanoseconds; for example to cope with failure mechanisms that could arise in new storage physics. Fast ECCs are also desired for eXecuted-in-Place (XiP) and DRAM applications. This paper shows the key elements to implement a BCH code able to correct 2 errors in a page of 256 data bits in no more than 10ns with 180nm-CMOS logic, and with low energy consumption. The decoding time can be further reduced to few ns using smaller gate length logics. Moreover, the proposed solution is soundly rooted in BCH theory, and can be applied to any user data size. Basically the ideas are to avoid the division in the computation of the coefficients of the Error Locator Polynomial (ELP) of the BCH code, to optimize the implementation of the multiplication in the Galois Fields (GF) and to fully implement the decoder in a parallel combinatorial architecture. Such a BCH code has been embedded in a 45nm 1Gbit Phase Change Memory (PCM) device.