Experimental study of programming saturation in low-coupling planar high-k/metal gate nand flash memory cells using a dedicated test structure

Fully planar NAND Flash arrays operate with very low coupling ratio (CR), and the CR reduces even further when scaling below 20 nm half-pitch. As a consequence, they suffer from programming saturation due to excessive leakage through the intergate dielectic (IGD) if no special precautions (such as the use of high-k IGD or hybrid floating gate) are taken. In this work, we investigate the dependence on the coupling ratio of programming saturation by using a dedicated test structure: by using a device with 8 wordlines sharing the same floating gate (FG), it is possible to program this device with any arbitrarily reduced effective coupling ratio, showing which programming window can be achieved. We demonstrate that the used devices with polySi\TiN FG and HfAlO\Al
₂
O
₃
\HfAlO IGD stack are suitable for operation with a coupling ratio down to 35% with 4V programming window above the fresh V
_th
. This coupling ratio corresponds to fully planar memory cells with 10 nm half-pitch, showing that programming saturation is not a showstopper for scaling down to 10nm node fully planar Flash memory cells.